Dynamic multi-core processor voltage scaling based on online core count

ABSTRACT

A device and method for controlling a voltage applied to processor cores of a processor are disclosed. The method includes processing a plurality of tasks on the processor with a plurality of processor cores and applying a rail voltage to the plurality of processor cores. The number of the plurality of processor cores that are active is adjusted, and the rail voltage that is applied to the plurality of processor cores is adjusted based upon the number of the plurality of processor cores that are active.

CLAIM OF PRIORITY UNDER 35 U.S.C. § 119

The present Application for Patent claims priority to ProvisionalApplication No. 62/119,716 entitled “DYNAMIC MULTI-CORE PROCESSORVOLTAGE SCALING BASED ON ONLINE CORE COUNT” filed Feb. 23, 2015 andassigned to the assignee hereof and hereby expressly incorporated byreference herein.

BACKGROUND

Field

The present disclosed embodiments relate generally to computing devices,and more specifically to control of power to processors.

Background

Computing devices including devices such as smartphones, tabletcomputers, gaming devices, and laptop computers are now ubiquitous.These communication devices are now capable of running a variety ofapplications (also referred to as “apps”) and many of these devicesinclude processors to process tasks that are associated with apps. Inmany instances, multiple cores are integrated as a collection ofprocessor cores within a single functional subsystem. It is known thatthe processing load on a mobile device may be apportioned to themultiple cores. As an example, for load balancing purposes, a processingtask may be migrated from one core to another core. In many existingdevices multiple cores operate at the same frequency; thus a particulartask may be migrated from one core to another core without substantiallyaffecting what the user experiences because the task is processed at thesame frequency regardless of the core.

In a system with a synchronous multi-core processor, in which all coresare powered by the same voltage supply, it is necessary for the voltageof the supply to be high enough to account for losses (e.g., voltagedrops in a power distribution network on the board and in the system ona chip (SoC)) as well as noise so that all cores can operatesuccessfully at the same time. But this voltage may be conservativelykept too high in situations where not all of the cores are active, whichleads to unnecessary, additional power consumption.

SUMMARY

According to an aspect, a computing device includes a plurality ofprocessor cores, a power rail coupled to the plurality of processorcores, and a power supply coupled to the power rail to apply a railvoltage to the processor cores via the power rail. An online-core-basedvoltage controller is coupled to the power supply, and theonline-core-based voltage controller is configured to control thevoltage applied by the power supply based on a number of the processorcores that are active.

Another aspect includes a method for controlling power that is appliedto a processor of a computing device. The method includes processing aplurality of tasks on the computing device with a plurality of processorcores, applying a shared rail voltage to the plurality of processorcores, and adjusting a number of the plurality of processor cores thatare active. The shared rail voltage that is applied to the plurality ofprocessor cores is adjusted based upon the number of the plurality ofprocessor cores that are active.

Yet another aspect includes a non-transitory, tangible processorreadable storage medium, encoded with processor readable instructions toperform a method for obtaining web content on a computing device. Themethod includes processing a plurality of tasks on the computing devicewith a plurality of processor cores, applying a rail voltage to theplurality of processor cores, and adjusting a number of the plurality ofprocessor cores that are active. The rail voltage that is applied to theplurality of processor cores is adjusted based upon the number of theplurality of processor cores that are active.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating components of a computing device;

FIG. 2 is a depiction of a voltage table that may be utilized to realizethe voltage table depicted in FIG. 1;

FIG. 3 is a flowchart depicting a method that may be traversed inconnection with the computing device depicted in FIG. 1; and

FIG. 4 is a block diagram depicting physical structures that may beutilized in connection with implementing the embodiments disclosedherein.

DETAILED DESCRIPTION

The word “exemplary” is used herein to mean “serving as an example,instance, or illustration.” Any embodiment described herein as“exemplary” is not necessarily to be construed as preferred oradvantageous over other embodiments.

Referring to FIG. 1, it is a block diagram illustrating components of acomputing system 100 (also referred to herein as a computing device100). The block diagram includes applications 102 (e.g., a web browser103) at the highest level of abstraction and hardware such as asynchronous multicore processor 114 (e.g., application processor), whichincludes a plurality of processor cores 116, at the lowest level. Asshown, in this embodiment, the processor cores 116 are coupled to apower supply 104 via a shared power rail 105; thus the processor cores116 in this embodiment share a rail voltage that is the sole voltageapplied by the power supply 104.

The kernel 108 along with interface 106 enable communication between theapplications 102 and the processor 114. In particular, the interface 106passes system calls from the applications 102 to the kernel 108. In anembodiment, the kernel 108 is realized by a LINUX kernel that has beenmodified as discussed further herein. Although the specific embodimentdepicted in FIG. 1 depicts multiple processor cores 116 within theprocessor 114, it should be recognized that other embodiments include aplurality of processors that are not integrated within a processor 114,but share a supply voltage. As a consequence, the operation of multipleprocessors is described herein in the context of both multiple processorcores 116, and more generally, multiple processors, which may includeprocessor cores and discrete CPUs that share a supply voltage.

The one or more applications 102 may be realized by a variety ofapplications that operate via, or run on, the processor 114 or anotherprocessor (not shown). For example, the one or more applications 102 mayinclude a web browser 103 and associated plug-ins, entertainmentapplications (e.g., video games, video players), productivityapplications (e.g., word processing, spread sheet, publishingapplications, video editing, photo editing applications), coreapplications (e.g., phone, contacts), and augmented realityapplications.

As one of ordinary skill in the art will appreciate, the user-space 130and kernel-space 132 components depicted in FIG. 1 may be realized byhardware in connection with processor-executable code stored in anon-transitory, tangible processor readable medium such as nonvolatilememory, and can be executed by the processor 114. Numerous variations onthe embodiments herein disclosed are also possible.

In general, the core controller 112 operates to vary the number ofprocessor cores 116 that are active (also referred to as online) basedupon the processing load that the processor 114 is required to process,and as shown, the core controller 112 provides an indication of thenumber active cores to an online-core-based voltage controller 110. Inaddition, the core controller 112 may also provide an indication of thecurrent operating frequency of the processor 114. In turn, theonline-core-based voltage controller 110 generally operates to control avoltage of the power rail 105 based upon the number of processor cores116.

In an embodiment, the online-core-based voltage controller 110 may berealized by processor-executable code stored in a non-transitory,tangible processor readable medium such as nonvolatile memory, and canbe executed by the processor 114. When the kernel 108 is realized bymodifying a LINUX kernel for example, the online-core-based voltagecontroller 110 may be realized as a software module that is incorporatedinto the LINUX kernel code and designed to work with the core controller112 and the power supply 104 via a driver for the power supply 104.

More specifically, the rail voltage of the processor 114 may be lowered,based upon the number of active cores, to reduce power that is appliedby the power supply 104. The adjustment amount may be determined by howmany processor cores 116 are online in addition to the current frequencyof operation of the processor 114. The adjustment may be performed inorder to safely remove voltage margin that was included in theworst-case, all-cores-online-voltage to account forpower-distribution-network losses and noise.

In some embodiments, the computing device 100 is characterized by aminimum voltage (Vmin) required to maintain a user-experience undervarious predefined operating conditions (e.g., operating frequency andnumber of active cores). In the embodiment depicted in FIG. 1, thecomputing device 100 includes a voltage table 111 that maps a pluralityof voltages a combination of an active core value and a frequency.

Referring briefly to FIG. 2, for example, shown is a voltage table 211that may be used to realize the voltage table 111 shown in FIG. 1. Asshown in FIG. 2, the characterization data produced by characterizingthe computing device 100 may be stored in the voltage table 211 for usein connection with the online-core-based voltage controller 110. Asshown for example, the voltage table 211 may map each of a plurality ofvoltage values to a combination of a frequency and an active core value.In this way, when the computing device 100 is in use, a particularvoltage (Vmin) may be selected based upon the current number of activecores and current frequency of the processor 114. The voltage table 211may be created using empirical data that is generated by testingvoltages in connection with combinations of operating frequency andactive online cores to determine voltage values that are applied by thepower supply 104.

Although not required, to generate the characterization data,comprehensive characterization may be performed across thousands ofdevices from an entire production process spectrum to determine a Vminrequired for each target frequency. As shown in FIG. 2, the targetfrequencies for characterization may be three frequency modes: turbo (ahighest frequency); nominal (a typical frequency); andstatic-voltage-scaling-mode (SVS)(a low voltage/lowest frequency mode).Although the depicted voltage table 211 shows that voltage values V1-V9are available for 1-core, 2-core, and 4-core modes of operation, this ismerely an example, and the number of active cores that may operate at aparticular time may vary depending upon the type of processor 114 thatis utilized on the computing device 100.

In terms of an actual reduction in rail voltage that may be realized, aparticular computing device operating at a particular frequency moderequired a Vmin when operating in a dual-core mode of operation that was60 mV higher than the Vmin required in a quad-core mode of operation.And when operating in a single-core mode, the particular device(operating in the particular frequency mode) required a Vmin that was 80mV less than Vmin in a quad-core mode of operation.

Referring next to FIG. 3, shown is a flowchart 300 representing a methodthat may be traversed in connection with the embodiment described withreference to FIG. 1. As shown, the plurality of processor cores 116operate to process various tasks in the computing device 100 (Block302). As one of ordinary skill in the art will appreciate, the tasks maybe associated with a variety of different types of executable filesincluding applications 102. As described with reference to FIG. 1, arail voltage is applied to the processor cores 116 (Block 304). In theembodiment depicted in FIG. 1, the processor cores 116 are synchronouslyoperated so that an operating frequency of all the processor cores 116is the same, but in many implementations the single operating frequencythat is utilized by all of the processor cores 116 may be adjusted tosave power while meeting the workload placed on the processor 114.

In addition, a number of the processor cores 116 that are active may beadjusted during operation (Block 306). For example, one or more of theprocessor cores 116 may be taken offline to save power when theprocessing load does not demand all of the processor cores 116 to beoperating. In response to the number of active processor cores 116changing, a voltage value for the rail voltage is obtained (Block 308).For example, the voltage value may be obtained from the voltage table111, 211.

As shown, after the voltage value is obtained, the online-core-basedvoltage controller 110 adjusts the rail voltage to the voltage value(e.g., one of the voltage values V1-V9 depicted in the voltage table).More specifically, if less than all of the processor cores 116 areactive, then the rail voltage may be reduced to save power. As discussedabove, the typical rail voltage (established for losses when all theprocessor cores 116 are online) need not be utilized when only a portionof the processor cores 116 is active.

The systems and methods described herein can be implemented in a machinesuch as a processor-based system in addition to the specific physicaldevices described herein. FIG. 4 shows a diagrammatic representation ofone embodiment of a machine in the exemplary form of a processor-basedsystem 400 within which a set of instructions can execute for causing adevice to perform or execute any one or more of the aspects and/ormethodologies of the present disclosure. The components in FIG. 4 areexamples only and do not limit the scope of use or functionality of anyhardware, software, embedded logic component, or a combination of two ormore such components implementing particular embodiments.

Processor-based system 400 may include processors 401, a memory 403, andstorage 408 that communicate with each other, and with other components,via a bus 440. The bus 440 may also link a display 432 (e.g., touchscreen display), one or more input devices 433 (which may, for example,include a keypad, a keyboard, a mouse, a stylus, etc.), one or moreoutput devices 434, one or more storage devices 435, and varioustangible storage media 436. All of these elements may interface directlyor via one or more interfaces or adaptors to the bus 440. For instance,the various non-transitory tangible storage media 436 can interface withthe bus 440 via storage medium interface 426. Processor-based system 400may have any suitable physical form, including but not limited to one ormore integrated circuits (ICs), printed circuit boards (PCBs), mobilehandheld devices (such as mobile telephones or PDAs), laptop or notebookcomputers, distributed computer systems, computing grids, or servers.

Processors 401 (or central processing unit(s) (CPU(s))) optionallycontain a cache memory unit 402 for temporary local storage ofinstructions, data, or computer addresses. Processor(s) 401 areconfigured to assist in execution of processor-executable instructions.Processor-based system 400 may provide functionality as a result of theprocessor(s) 401 executing software embodied in one or more tangibleprocessor-readable storage media, such as memory 403, storage 408,storage devices 435, and/or storage medium 436. The processor-readablemedia may store software that implements particular embodiments, andprocessor(s) 401 may execute the software. Memory 403 may read thesoftware from one or more other processor-readable media (such as massstorage device(s) 435, 436) or from one or more other sources through asuitable interface, such as network interface 420. The software maycause processor(s) 401 to carry out one or more processes or one or moresteps of one or more processes described or illustrated herein. Carryingout such processes or steps may include defining data structures storedin memory 403 and modifying the data structures as directed by thesoftware.

The memory 403 may include various components (e.g., machine readablemedia) including, but not limited to, a random access memory component(e.g., RAM 404) (e.g., a static RAM “SRAM”, a dynamic RAM “DRAM, etc.),a read-only component (e.g., ROM 405), and any combinations thereof. ROM405 may act to communicate data and instructions unidirectionally toprocessor(s) 401, and RAM 404 may act to communicate data andinstructions bidirectionally with processor(s) 401. ROM 405 and RAM 404may include any suitable tangible processor-readable media describedbelow. In one example, a basic input/output system 406 (BIOS), includingbasic routines that help to transfer information between elements withinprocessor-based system 400, such as during start-up, may be stored inthe memory 403.

Fixed storage 408 is connected bidirectionally to processor(s) 401,optionally through storage control unit 407. Fixed storage 408 providesadditional data storage capacity and may also include any suitabletangible processor-readable media described herein. Storage 408 may beused to store operating system 409, EXECs 410 (executables), data 411,applications 412 (application programs), and the like. Often, althoughnot always, storage 408 is a secondary storage medium (such as a harddisk) that is slower than primary storage (e.g., memory 403). Storage408 can also include an optical disk drive, a solid-state memory device(e.g., flash-based systems), or a combination of any of the above.Information in storage 408 may, in appropriate cases, be incorporated asvirtual memory in memory 403.

In one example, storage device(s) 435 may be removably interfaced withprocessor-based system 400 (e.g., via an external port connector (notshown)) via a storage device interface 425. Particularly, storagedevice(s) 435 and an associated machine-readable medium may providenonvolatile and/or volatile storage of machine-readable instructions,data structures, program modules, and/or other data for theprocessor-based system 400. In one example, software may reside,completely or partially, within a machine-readable medium on storagedevice(s) 435. In another example, software may reside, completely orpartially, within processor(s) 401.

Bus 440 connects a wide variety of subsystems. Herein, reference to abus may encompass one or more digital signal lines serving a commonfunction, where appropriate. Bus 440 may be any of several types of busstructures including, but not limited to, a memory bus, a memorycontroller, a peripheral bus, a local bus, and any combinations thereof,using any of a variety of bus architectures. As an example and not byway of limitation, such architectures include an Industry StandardArchitecture (ISA) bus, an Enhanced ISA (EISA) bus, a Micro ChannelArchitecture (MCA) bus, a Video Electronics Standards Association localbus (VLB), a Peripheral Component Interconnect (PCI) bus, a PCI-Express(PCI-X) bus, an Accelerated Graphics Port (AGP) bus, HyperTransport(HTX) bus, serial advanced technology attachment (SATA) bus, and anycombinations thereof.

Processor-based system 400 may also include an input device 433. In oneexample, a user of processor-based system 400 may enter commands and/orother information into processor-based system 400 via input device(s)433. Examples of an input device(s) 433 include, but are not limited to,an alpha-numeric input device (e.g., a keyboard), a pointing device(e.g., a mouse or touchpad), a touchpad, a joystick, a gamepad, an audioinput device (e.g., a microphone, a voice response system, etc.), anoptical scanner, a video or still image capture device (e.g., a camera),and any combinations thereof. Input device(s) 433 may be interfaced tobus 440 via any of a variety of input interfaces 423 (e.g., inputinterface 423) including, but not limited to, serial, parallel, gameport, universal serial bus (USB), FIREWIRE, THUNDERBOLT, or anycombination of the above.

In particular embodiments, when processor-based system 400 is connectedto network 430, processor-based system 400 may communicate with otherdevices, specifically mobile devices and enterprise systems, connectedto network 430. Communications to and from processor-based system 400may be sent through network interface 420. For example, networkinterface 420 may receive incoming communications (such as requests orresponses from other devices) in the form of one or more packets (suchas Internet Protocol (IP) packets) from network 430, and processor-basedsystem 400 may store the incoming communications in memory 203 forprocessing. Processor-based system 400 may similarly store outgoingcommunications (such as requests or responses to other devices) in theform of one or more packets in memory 403 and communicated to network430 from network interface 420. Processor(s) 401 may access thesecommunication packets stored in memory 403 for processing.

Examples of the network interface 420 include, but are not limited to, anetwork interface card, a modem, and any combination thereof. Examplesof a network 430 or network segment 430 include, but are not limited to,a wide area network (WAN) (e.g., the Internet, an enterprise network), alocal area network (LAN) (e.g., a network associated with an office, abuilding, a campus or other relatively small geographic space), atelephone network, a direct connection between two computing devices,and any combinations thereof. A network, such as network 230, may employa wired and/or a wireless mode of communication. In general, any networktopology may be used.

Information and data can be displayed through a display 432. Examples ofa display 422 include, but are not limited to, a liquid crystal display(LCD), an organic light emitting diode (OLED) display, a cathode raytube (CRT), a plasma display, and any combinations thereof. The display432 can interface to the processor(s) 401, memory 403, and fixed storage408, as well as other devices, such as input device(s) 433, via the bus440. The display 432 is linked to the bus 440 via a video interface 422,and transport of data between the display 432 and the bus 440 can becontrolled via the graphics control 421.

In addition to a display 432, processor-based system 400 may include oneor more other peripheral output devices 434 including, but not limitedto, an audio speaker, a printer, and any combinations thereof. Suchperipheral output devices may be connected to the bus 440 via an outputinterface 424. Examples of an output interface 424 include, but are notlimited to, a serial port, a parallel connection, a USB port, a FIREWIREport, a THUNDERBOLT port, and any combinations thereof.

In addition or as an alternative, processor-based system 400 may providefunctionality as a result of logic hardwired or otherwise embodied in acircuit, which may operate in place of or together with software toexecute one or more processes or one or more steps of one or moreprocesses described or illustrated herein. Reference to software in thisdisclosure may encompass logic, and reference to logic may encompasssoftware. Moreover, reference to a processor-readable medium mayencompass a circuit (such as an IC) storing software for execution, acircuit embodying logic for execution, or both, where appropriate. Thepresent disclosure encompasses any suitable combination of hardware,software, or both.

Those of skill in the art would understand that information and signalsmay be represented using any of a variety of different technologies andtechniques. For example, data, instructions, commands, information,signals, bits, symbols, and chips that may be referenced throughout theabove description may be represented by voltages, currents,electromagnetic waves, magnetic fields or particles, optical fields orparticles, or any combination thereof.

Those of skill would further appreciate that the various illustrativelogical blocks, modules, circuits, and algorithm steps described inconnection with the embodiments disclosed herein may be implemented aselectronic hardware, or hardware in connection with software. Variousillustrative components, blocks, modules, circuits, and steps have beendescribed above generally in terms of their functionality. Whether suchfunctionality is implemented as hardware or hardware that utilizessoftware depends upon the particular application and design constraintsimposed on the overall system. Skilled artisans may implement thedescribed functionality in varying ways for each particular application,but such implementation decisions should not be interpreted as causing adeparture from the scope of the present invention.

The various illustrative logical blocks, modules, and circuits describedin connection with the embodiments disclosed herein may be implementedor performed with a general purpose processor, a digital signalprocessor (DSP), an application specific integrated circuit (ASIC), afield programmable gate array (FPGA) or other programmable logic device,discrete gate or transistor logic, discrete hardware components, or anycombination thereof designed to perform the functions described herein.A general purpose processor may be a microprocessor, but in thealternative, the processor may be any conventional processor,controller, microcontroller, or state machine. A processor may also beimplemented as a combination of computing devices, e.g., a combinationof a DSP and a microprocessor, a plurality of microprocessors, one ormore microprocessors in conjunction with a DSP core, or any other suchconfiguration.

The steps of a method or algorithm described in connection with theembodiments disclosed herein may be embodied directly in hardware, in asoftware module executed by a processor, or in a combination of the two.A software module may reside in random access memory (RAM), flashmemory, read only memory (ROM), erasable programmable read-only memory(EPROM), electrically erasable programmable read-only memory (EEPROM),registers, hard disk, a removable disk, a CD-ROM, or any other form ofstorage medium known in the art. An exemplary storage medium is coupledto the processor such the processor can read information from, and writeinformation to, the storage medium. In the alternative, the storagemedium may be integral to the processor. The processor and the storagemedium may reside in an ASIC. The ASIC may reside in a user terminal. Inthe alternative, the processor and the storage medium may reside asdiscrete components in a user terminal.

The previous description of the disclosed embodiments is provided toenable any person skilled in the art to make or use the presentinvention. Various modifications to these embodiments will be readilyapparent to those skilled in the art, and the generic principles definedherein may be applied to other embodiments without departing from thespirit or scope of the invention. Thus, the present invention is notintended to be limited to the embodiments shown herein but is to beaccorded the widest scope consistent with the principles and novelfeatures disclosed herein.

What is claimed is:
 1. A computing device comprising: a plurality ofprocessor cores: a power rail coupled to the plurality of processorcores; a power supply coupled to the power rail to apply a rail voltageto the processor cores via the power rail; a kernel configured tocommunicate with the plurality of processor cores, the power supply, andapplications of the computing device, the kernel is configured toreceive system calls from the applications, and the kernel includes: acore controller configured to first control a frequency of the processorcores and a number of processor cores that are online based upon aprocessing load that is placed on the plurality of processor cores bytasks associated with the applications; an online-core-based voltagecontroller configured to receive, from the core controller, both anindication of the number of processor cores that are online and afrequency of the processor cores, and the online-core-based voltagecontroller is configured to control, via a driver of the kernel, andafter the core controller controls the frequency of the processor cores,the rail voltage applied by the power supply based on the number ofprocessor cores that are online and the frequency of the processorcores; and a voltage table that maps each of an active core value to oneof a turbo frequency mode, a nominal frequency mode, or astatic-voltage-scaling frequency mode, wherein each frequency mode ismapped to a corresponding one of a plurality of minimum voltage values;wherein the online-core-based voltage controller is configured to:obtain a particular minimum voltage value from the voltage table basedon the number of processor cores that are online and the frequency modeof the processor cores; and adjust the rail voltage to the particularminimum voltage value.
 2. The computing device of claim 1, wherein allof the plurality of processor cores operate at a same frequency and at asame voltage.
 3. The computing device of claim 1, wherein the power railis a sole power rail applying power to the plurality of processor coresand the rail voltage is a sole voltage applied to the plurality ofprocessor cores.
 4. The computing device of claim 1, whereincharacterization data of the computing device provides the minimumvoltage values stored in the voltage table.
 5. The computing device ofclaim 4, wherein the characterization data is obtained fromcharacterization tests across a plurality of identical computing devicesto the computing device.
 6. A method for controlling power that isapplied to a processor of a computing device, the method comprising:receiving system calls at a kernel of the computing device fromapplications on the computing device; processing a plurality of tasksassociated with the applications on the computing device with aplurality of processor cores; applying a rail voltage to the pluralityof processor cores with a power supply of the computing device;adjusting first, with a core controller of the kernel, a frequency ofthe plurality of processor cores and a number of the plurality ofprocessor cores that are active based upon a processing load that isplaced on the plurality of processor cores by the plurality of tasks;adjusting, via a driver of the kernel, and after the core controlleradjusts the frequency of the plurality of processor cores, with anonline-core-based voltage controller of the kernel, the rail voltagethat is applied by the power supply to the plurality of processor coresbased upon the frequency and the number of the plurality of processorcores that are active; obtaining a particular minimum voltage value froma voltage table that maps each of an active core value to one of a turbofrequency mode, a nominal frequency mode, or a static-voltage scalingfrequency mode, wherein each frequency mode is mapped to a correspondingone of a plurality of minimum voltage values; setting anall-cores-online-voltage to a value to provide a minimum voltage to theprocessor cores, plus a margin, based upon losses and noise; andadjusting the rail voltage to the particular minimum voltage valuewherein the rail voltage is set to a value that is less than theall-cores-online-voltage value when less than all of the processor coresare active.
 7. The method of claim 6, wherein the number of theplurality of processor cores that are active is adjusted based upon aprocessing load that is placed on the plurality of processor cores. 8.The method of claim 6, further comprising: providing characterizationdata comprising the minimum voltage values stored in the voltage table.9. The method of claim 8, further comprising: generating thecharacterization data by performing characterization tests across aplurality of identical computing devices to the computing device.
 10. Anon-transitory, tangible processor readable storage medium, encoded withprocessor readable instructions to perform a method for controllingpower that is applied to a processor on a computing device, the methodcomprising: receiving system calls at a kernel of the computing devicefrom applications on the computing device; processing a plurality oftasks associated with the applications on the computing device with aplurality of processor cores; applying a rail voltage to the pluralityof processor cores with a power supply of the computing device;adjusting first, with a core controller of the kernel, a frequency ofthe plurality of processor cores and a number of the plurality ofprocessor cores that are active based upon a processing load that isplaced on the plurality of processor cores by the plurality of tasks;adjusting, via a driver of the kernel, and after the core controlleradjusts the frequency of the plurality of processor cores, with anonline-core-based voltage controller of the kernel, the rail voltagethat is applied by the power supply to the plurality of processor coresbased upon the frequency and the number of the plurality of processorcores that are active obtaining a particular minimum voltage value froma voltage table that maps each of an active core value to one of a turbofrequency mode, a nominal frequency mode, or a static-voltage-scalingfrequency mode wherein each frequency mode is mapped to a correspondingone of a plurality of minimum voltage values; setting anall-cores-online-voltage to a value to provide a minimum voltage to theprocessor cores, plus a margin, based upon losses and noise; andadjusting the rail voltage to the particular minimum voltage valuewherein the rail voltage is set to a value that is less than theall-cores-online-voltage value when less than all of the processor coresare active.
 11. The non-transitory, tangible processor readable storagemedium of claim 10, wherein the number of the plurality of processorcores that are active is adjusted based upon a processing load that isplaced on the plurality of processor cores.